Design example

M$_1$ and M$_2$ in Figs. 4, 5 and 6 produce a distortion caused by a variation of transconductance. The proposed distortion reduction technique is applied to these MOSFETs whose gate-to-source voltages are varied.

First, the proposed technique is applied to Fig. 4 and a novel low distortion active inductor is derived. It is obvious that a gate-to-source voltage of M$_1$ is varied more widely than that of M$_2$ because a gate-to-source voltage of M$_1$ is amplified by M$_2$ which acts as a common source amplifier. Therefore applying the proposed technique to the M$_1$ is more effective. Figure 7(b) is suitable for M$_1$ because the output current of M$_1$ flows out from its source terminal. A bias current source M$_3$ is able to be used to realize compensation current $I_c$. A gate-to-source voltage of M$_3$ is controlled to be $V_{bias}-v_{gs1}$ where $V_{bias}$ and $v_{gs1}$ is a bias voltage and variation of gate-to-source voltage of M$_1$. Fig. 8 shows the proposed low distortion active inductor. It consists of Fig. 4 and two level shift circuits. A level shift circuit, M$_5$ and M$_6$, outputs a voltage which is equal to a gate-to-source voltage of M$_1$. Another level shift circuit, M$_7$ and M$_8$, subtracts the voltage from $V_{g7}$ and outputs $V_{g7}-V_{gs1}-v_{gs1}$. This output voltage is used for the gate-to-source voltage of M$_3$. Thanks to these two level shift circuits the gate-to-source voltage of M$_3$ becomes $V_{bias}-v_{gs1}$. When $V_{g7}$ is equal to $2V_{gs1}$ the gate-to-source voltage of M$_3$ becomes $V_{gs1}-v_{gs1}$. Elements in the equivalent circuit of Fig. 8 become

$$G_{p} = g_{m2}+g_{ds1}+g_{ds2}+g_{ds3}+g_{ds4}$$

$$C_{p} = C_{gs2}$$

$$R_{s} = \frac{g_{ds2}+g_{ds4}}{(2g_{m1}-g_{ds2}-g_{ds4})(g_{m2}+g_{ds2}+g_{ds4})}$$

$$L = \frac{C_{gs1}}{(2g_{m1}-g_{ds2}-g_{ds4})(g_{m2}+g_{ds2}+g_{ds4})} .$$ (15)

When it is assumed that all $g_{ds}$ is much smaller than $g_{m}$, $L$ and $R_s$ is half of that of Fig. 8.

Figure 8: Active inductor with the proposed distortion reduction circuit

Second, another low distortion active inductor is derived from Fig. 6. The proposed technique is applied to M$_2$ which acts as a common source amplifier because load of M$_1$ is large and the output voltage of the common gate amplifier M$_1$, which is input voltage of M$_2$, also becomes large. M$_2$ is replaced by Fig. 7(a) in order to suppress distortion occurs at M$_2$. Figure 9 is a proposed low distortion active inductor derived from Fig. 6. A compensation current source M$_5$ is inserted in parallel with a bias current source. The sum of gate-to-source voltage of M$_2$ and M$_5$ is kept constant since the source terminal of M$_5$ is connected to the gate of M$_2$. When a gate-to-source voltage of M$_2$ is $V_{gs2}+v_{gs2}$ a gate-to-source voltage of M$_5$ becomes

$$V_{gs5} = V_{G5}-V_{gs2}-v_{gs2}$$ (16)

and the drain current of M$_5$ acts as $I_c$.

Figure 9: Proposed low distortion active inductor using M$_5$

Even when the source terminal of M$_5$ is connected to the drain terminal of M$_1$ instead of the drain terminal of M$_2$, the proposed subtraction of $I_D$ and $I_c$ is achieved correctly. Insertion of M$_5$ is very simple and effective in improving linearity, however, it enlarge parallel resistance $R_s$. Unfortunately a large $R_s$ limits lower limit of available frequency range of an active inducer as shown in Eq.(3). Another low distortion active inductor which prevents this problem is shown in Fig. 10. M$_4$ is used for a compensation current source in Fig. 10. Perfect matching a transconductance parameter $K$ of M$_4$ to that of M$_2$ is difficult because channel types of M$_4$ and M$_2$ are different. However, careful design can minimize the mismatch and distortion occurs at M$_2$ is suppressed.

Figure 10: Proposed low distortion active inductor using M$_4$